Primary resonant flyback converters

ABSTRACT

A primary resonant flyback converter may include a primary winding, a resonant capacitor in series with the primary winding, a secondary winding magnetically coupled to the primary winding, and an output electrically coupled to the secondary winding. A main switch may be operated to energize the primary winding when closed and transfer energy stored in the primary winding to the secondary winding when open. An auxiliary switch may be configured to switch complimentarily to the main switch, thereby allowing a resonant current to circulate through the primary winding and capacitor. Switch timing may be controlled to produce a desired output voltage. The converter may also include an input inductor that receives an input voltage, presenting an improved power factor to an AC input power source and in conjunction with the switching devices boosts a rectified AC input voltage to a DC voltage bus of the converter.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a division of U.S. patent application Ser. No.15/718,936, filed Sep. 28, 2017, entitled “Power Factor CorrectedPrimary Resonant Flyback Converters, by InHwan Oh, et al., which claimspriority to U.S. Provisional Application No. 62/538,135, filed Jul. 28,2017, entitled “Primary Resonant Flyback Converters,” by InHwan Oh, etal., U.S. Provisional Application No. 62/538,146, filed Jul. 28, 2017,entitled Primary Resonant Flyback Converters,” by InHwan Oh, and U.S.Provisional Application No. 62/538,156, filed Jul. 28, 2017, entitled“Primary Resonant Flyback Converters,” by InHwan Oh, et al., all ofwhich are incorporated by reference herein in their entireties.

BACKGROUND

Conventional flyback converters are widely used to convert a highvoltage AC input (e.g., 90 VAC to 265 Vac) to a low voltage DC output(e.g., 5 VDC to 20 VDc) because they are simple circuits and may beconstructed inexpensively due to a relatively low number of components.One drawback to conventional flyback converters is that the powerconversion efficiency is typically around 80˜85% for 20 W output powerrange. Significant sources of power loss in conventional flybackconverters include switching losses caused by activating the switchingcomponents when both voltage and current are high. Another disadvantageof conventional flyback converters, in at least some embodiments, isthat the primary and secondary side current waveforms are saw toothtype, which include high frequency harmonics. Thus, it may be desirableto provide improved flyback converters that reduce these switchinglosses and harmonic components as well as providing other beneficialcharacteristics.

SUMMARY

A primary resonant flyback converter may include a primary winding and asecondary winding magnetically coupled thereto, with an output of theconverter being electrically coupled to the secondary winding. The powerconverter may also include a resonant capacitor in series with theprimary winding. A main switch may be configured to switch so that whenclosed the main switch energizes the primary winding and resonantcapacitor from a DC voltage bus and when open the energy stored in theprimary winding and resonant capacitor is transferred to the secondarywinding. The converter may also include an auxiliary switch configuredto switch on during an off time of the main switch and switch off duringan on time of the main switch, thereby allowing a resonant current tocirculate through the primary winding and the resonant capacitor. Thetiming of the main (and auxiliary) switch(es) may be altered to producea desired voltage at the output of the power converter. The convertermay also include an input inductor that receives an input voltage, andpresents an improved power factor to an AC input power source. Thisinput inductor may also, in conjunction with at least one of theswitches and a body diode of at least one of the switches, function as aboost converter to boost a rectified AC input voltage to the DC voltagebus of the converter.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a schematic diagram of a primary resonant flybackconverter.

FIG. 2 illustrates a switching sequence of a primary resonant flybackconverter.

FIG. 3 illustrates selected waveforms of a primary resonant flybackconverter.

FIG. 4 illustrates two alternative schematic diagrams of primaryresonant flyback converters.

FIG. 5 illustrates a schematic diagram of a full bridge primary resonantflyback converter.

FIG. 6 illustrates a schematic diagram of a primary resonant flybackconverter with primary side voltage sensing and control.

FIG. 7 illustrates two stages of the switching cycle associated withprimary side voltage sensing in a primary resonant flyback converter.

FIG. 8 illustrates a flowchart of a control algorithm for a primaryresonant flyback converter.

FIG. 9 illustrates a primary resonant flyback converter with losslesscurrent sensing on the primary side.

FIGS. 10A and 10B illustrate selected waveforms relating to losslesscurrent sensing on the primary side.

FIG. 11 illustrates a schematic diagram of a primary resonant flybackconverter incorporating variable frequency control.

FIGS. 12A and 12B illustrate flowchart of variable frequency controlalgorithms.

FIG. 13 illustrates selected waveforms of a primary resonant flybackconverter incorporating burst mode operation.

FIG. 14 illustrates selected waveforms of a primary resonant flybackconverter incorporating burst mode operation with soft starting of theburst mode.

FIG. 15 illustrates a flowchart for a burst mode control algorithm.

FIG. 16 illustrates a schematic diagram of a power factor correctedprimary resonant flyback converter.

FIG. 17 illustrates a switching sequence of a power factor correctedprimary resonant flyback converter.

FIG. 18 illustrates selected waveforms of a power factor correctedprimary resonant flyback converter.

DETAILED DESCRIPTION

In the following description, for purposes of explanation, numerousspecific details are set forth to provide a thorough understanding ofthe disclosed concepts. As part of this description, some of thisdisclosure's drawings represent structures and devices in block diagramform for sake of simplicity. In the interest of clarity, not allfeatures of an actual implementation are described in this disclosure.Moreover, the language used in this disclosure has been selected forreadability and instructional purposes, has not been selected todelineate or circumscribe the disclosed subject matter. Rather theappended claims are intended for such purpose.

Various embodiments of the disclosed concepts are illustrated by way ofexample and not by way of limitation in the accompanying drawings inwhich like references indicate similar elements. For simplicity andclarity of illustration, where appropriate, reference numerals have beenrepeated among the different figures to indicate corresponding oranalogous elements. In addition, numerous specific details are set forthin order to provide a thorough understanding of the implementationsdescribed herein. In other instances, methods, procedures and componentshave not been described in detail so as not to obscure the relatedrelevant function being described. References to “an,” “one,” or“another” embodiment in this disclosure are not necessarily to the sameor different embodiment, and they mean at least one. A given figure maybe used to illustrate the features of more than one embodiment, or morethan one species of the disclosure, and not all elements in the figuremay be required for a given embodiment or species. A reference number,when provided in a given drawing, refers to the same element throughoutthe several drawings, though it may not be repeated in every drawing.The drawings are not to scale unless otherwise indicated, and theproportions of certain parts may be exaggerated to better illustratedetails and features of the present disclosure.

I. Primary Resonant Flyback Converter Topology

Disclosed herein are a variety of power converter embodiments based onthe primary resonant flyback converter topology. Primary resonantflyback converters are also known as asymmetric flyback converters orresonant flyback converters. One characteristic of a primary resonantflyback converter topology is a flyback mode of operation, meaning thatenergy is stored in the magnetic component during a first portion of theswitching cycle and then transferred to the load during a second portionof the switching cycle (as will be described in greater detail below).An additional characteristic is that the primary side of the circuitresonates, as described in greater detail below. Advantages of theprimary resonant flyback converter over conventional flyback convertersinclude zero voltage switching, which leads to increased operatingefficiency, and quasi-sinusoidal secondary current, which leads toreduced EMI and harmonic content. These advantages, including theincrease in efficiency, can allow for higher power density, smaller formfactors, and lower temperature stresses on the various components of theconverter.

An exemplary primary resonant flyback converter 100 implemented usingthis topology is illustrated in FIG. 1. More specifically, converter 100is a half bridge primary resonant flyback converter. (Full bridgeprimary resonant flyback converters are described below.) Converter 100converts high voltage alternating current (AC) electricity, deliveredfrom input power source 101 (such as 110V AC power mains in the US or220 V AC power mains in Europe), to a lower direct current (DC) voltagesuitable for delivery to a load (not shown). The load may include suchelectronic devices as a personal computer, notebook computer, tabletcomputer, smart phone, peripheral for one of the foregoing, etc.). Thelow voltage DC electricity can be delivered to the load via outputterminal 102.

Full bridge rectifier 103 at the input of converter 100 receives the ACinput power and converts it to a DC voltage that is delivered to a DCvoltage bus 104. Although a full bridge rectifier made up of four diodesis illustrated, other rectifier topologies could also be used. Examplesof such rectifier topologies can include various full bridge or halfbridge circuits made up of diodes, silicon controlled rectifiers (SCRs),or transistor switching devices. In the illustrated embodiment, DCvoltage bus 104 is supported by DC bus capacitor 105. The rectifiedinput voltage thus charges input capacitor 105 to a DC voltage bus levelV_(DC).

The primary side of converter 100 includes two switching devices, a mainswitch 106 and an auxiliary switch 107, a primary coil 108, and aresonant capacitor 109. Main switch 106 has a first terminal coupled toDC voltage bus 104 and a second terminal coupled to a first terminal ofauxiliary switch 107. A second terminal of auxiliary switch 107 iscoupled to ground. Additionally, primary coil 108 has a first terminalcoupled to the connection point of main switch 106 and auxiliary switch107. Thus, the first terminal of primary coil 108 may be coupled to theDC voltage bus 104 by main switch 106 or may be coupled to ground by theauxiliary switch. A second terminal of primary coil 108 is coupled to afirst terminal of resonant capacitor 109, which has its second terminalcoupled to ground. A third terminal of main switching device 106 and athird terminal of auxiliary switching device 107 may be coupled to acontroller 110, which can act as a driver to operate the switches toprovide resonant flyback operation as described in further detail below.

In some embodiments, main switch 106 and auxiliary switch 107 may beimplemented as metal-oxide semiconductor field effect transistors(MOSFETs). In other embodiments, other switching devices, such asjunction field effect transistors (JFETs), bipolar junction transistors(BJTs), insulated gate bipolar transistors (IGBTs), etc. could also beused. Additionally, resonant capacitor 109 may have multiple functions,including being used with primary coil 108 to provide resonant operationand also serving as a DC current block to prevent continuous DC currentflow through the circuit in the event of a failure of main switch 106.Such DC current flow could result in further damage, blown fuses orcircuit breakers, etc.

The secondary side of converter 100 includes secondary coil 111 andrectifier 112. Secondary coil 111 is magnetically coupled to primarycoil 108. Primary coil 108 and secondary coil 111 may be primary andsecondary windings of a transformer or may be any other type of mutuallycoupled inductors. Rectifier 112 may be implemented in a variety ofways. In some embodiments, rectifier 112 may be simply a diode. In otherembodiments, such as that illustrated in FIG. 1, rectifier 112 may beimplemented as a synchronous rectifier. As alluded to above, thesecondary side of converter 100 also includes output terminal 102, whichdelivers the converted low voltage DC electricity to the load.

In addition to the secondary coil 111 and rectifier 112, the secondaryside of converter 100 may also include an output voltage sensing andcontrol loop 113. As will be explained in greater detail below, thissecondary side control loop is optional, and may be replaced by aprimary side control loop. If secondary side control loop 113 isincluded, it will generally include voltage sensing circuitry 113 acoupled to output terminal 102, which will allow sensing and control ofthe output voltage of converter 100. Voltage sensing circuitry 113 a maybe implemented by a variety of digital, analog, and/or hybrid (i.e.,combined digital and analog) circuitry. This sensed output voltage willbe input into a control loop 113 b, which will implement a feedbacksignal 114 that is communicated to controller 110 for use in generatingthe drive signals for main switch 106 and auxiliary switch 107 (asdescribed in greater detail below). In general, the controller will varythe switching frequency and/or switch on and switch off times to producethe desired output voltage. Control loop 113 b may be implemented by avariety of digital, analog, and/or hybrid circuitry, including analogcontrol loops, digital controllers, application specific integratedcircuits (ASICs), and the like.

In some embodiments, control signal 114 will be communicated tocontroller 110 via an optocoupler 115, which allows for galvanicisolation between the primary and secondary sides. In some embodiments,rather than including voltage sensing circuitry 113 a and control loopcircuitry 113 b on the secondary side, control loop circuitry 113 b mayinstead be incorporated in controller 110 on the primary side, and thesignal fed back controller 110 will instead be the sensed outputvoltage. In still other embodiments (described below), the outputvoltage may be sensed by controller 110 by sensing the reflected outputvoltage appearing across the resonant capacitor 109 on the primary side.

Generally, main switch 106 may be controlled using conventional peakcurrent mode control with current regulated pulse width modulation.Auxiliary switch 107 may be driven complimentarily to main switch 106(i.e., driven with the opposite signal of main switch 106, with someintervening dead time to prevent cross conduction). Both switches may beturned ON with a zero voltage switching condition where the switches'drain to source voltages become zero before a gate signal is applied.This results in zero turn on losses for the switches. Primary coil 108may excited when main switch 106 is on. If main switch 106 is off andauxiliary witch 107 is on, the primary side circuit (i.e., primary coil108 and resonant capacitor 109) resonates with energy stored in theleakage inductance and magnetizing inductance of primary coil 108 duringthe excitation phase.

As a result of this resonance, energy stored in the leakage inductanceis circulated, recycled, and delivered to the secondary side circuit.Because energy stored in the leakage inductance is not dissipated,efficiency of the circuit is improved. Voltage stresses on main switch106 and auxiliary switch 107 are well clamped and limited by DC busvoltage 104 without any added snubber or clamping circuit. Thus, theprimary side circuit does not require a snubber circuit (as used inconventional flyback converters) to clamp voltage spikes. Additionally,because the resonance takes place while auxiliary switch 107 is on, thesecondary current waveform becomes quasi-sinusoidal, starting and endingsmoothly, and thereby reducing electromagnetic interference and harmonicdistortion.

FIG. 2 includes nine schematics 200-208 illustrating the switchingsequence for primary resonant flyback converter operation of converter100. Schematic 200 corresponds to the same state as 208, meaning thatslightly more than one switching cycle is illustrated. In each ofschematics 200-208, main switch 106 and auxiliary switch 108 aredepicted as an equivalent circuit of a MOSFET, including an idealswitch, a body diode, and a drain to source parasitic capacitancecoupled in parallel. Additionally, rectifier 112 is depicted as a diode(rather than a synchronous rectifier). Additionally each schematicdepicts the load 220 and the output capacitance 221 of converter 100.

Additionally, FIG. 3 depicts timing diagrams corresponding to theschematics depicted in FIG. 2. More specifically, FIG. 3 depicts gatedrive signal 301 for main switch 106 and gate drive signal 302 forauxiliary switch 107. As will be discussed in greater detail below, mainswitch 106 turns on at time t₀ and off at time t₂. Auxiliary switchturns on at time t₃ and turns off at time t₅. Time t₂ (where main switch106 turns off) and time t₃ (where auxiliary switch 107 turns on) areseparated by a short dead time t_(dead), which is interposed to preventcross conduction. (Dead time t_(dead) is discussed in further detailbelow.) After auxiliary switch 107 turns off at time t₅, and anothershort dead time, main switch 106 is turned on again at time t₆. The timeperiod between successive turn on events for main switch 106 are acomplete switching period or cycle T_(sw). Also depicted in FIG. 3 arethe primary current 303, the secondary current 304, and voltage 305 atthe junction between main switch 106 and auxiliary switch 107, which mayalso be thought of as the voltage appearing across auxiliary switch 107.

Beginning at time t₀ in schematic 201, main switch 106 closes under zerovoltage switching while primary current 210 is flowing in the indicatedpath. More specifically, current 210 is flowing from the ground side ofconverter 100, through series capacitance 109 and primary coil 108,through the body diode of main switch 106 to DC voltage bus 104. Becauseprimary current 210 is flowing through the body diode of main switch106, there is zero voltage across the main switch, which allows for zerovoltage switching of the main switch. Zero voltage switching of the mainswitch results in decreased switching losses.

Beginning at time t₁, illustrated in schematic 202, main switch 106 hasclosed. This establishes a current path for primary current 212 from theDC voltage bus 104, through the main switch 106, through primary coil106, through series capacitance 109, to ground. This primary current 212causes energy to be stored in the magnetic field associated with primarycoil 108 (and secondary coil 109).

At time t₂, main switch 106 is opened, as illustrated in schematic 203.Opening main switch 106 causes a circulating current 213 a to flow onthe primary side of converter 100. More specifically, even though mainswitch 106 has opened, the inductance of primary coil 108 tends to keepcurrent flowing in the same direction. Thus, primary current 213 acontinues momentarily in the same direction as primary current 212,which discharges the parasitic capacitance associated with auxiliaryswitch 107. Additionally, secondary current 213 b begins to flow throughsecondary coil 111, through rectifier 112, beginning the cycle ofdelivering energy stored in the magnetic field associated with primarycoil 108 and secondary coil 111 to load 220. Very shortly thereafter,when the parasitic capacitance of auxiliary switch 107 is discharged,the body diode associated with auxiliary switch 107 becomes forwardbiased, allowing circulating primary current 214 a to flow through thebody diode as illustrated in schematic 204. During this time, secondarycurrent 214 b continues to flow, continuing delivery of the energystored in the magnetic fields of primary coil 108 and secondary coil 111to load 220.

At time t₃, illustrated in schematic 205, auxiliary switch 107 closesunder zero voltage switching. Zero voltage switching is possible becausethe circulating current 214 a through the body diode of auxiliary switch107 (illustrated in schematic 204) results in zero voltage acrossauxiliary switch 107. Thus, as illustrated in schematic 205, circulatingprimary current 215 a flows through main switch 107, primary coil 108,and series capacitance 109. During this time, secondary current 215 bcontinues to flow as described above.

Primary coil 108 and series capacitance 109 form a series resonantcircuit. The series resonance will cause primary circulating current 215a to reverse direction at time t₄, thereby becoming primary reversecirculating current 216 illustrated in schematic 206.

As illustrated in schematic 207, at time t₅, once the energy stored inthe magnetic field associated with primary coil 108 and secondary coil111 has been delivered to load 220, auxiliary switch opens. Althoughauxiliary switch 107 has opened, the inductance of primary coil 108tends to keep current flowing in the same direction, thus current 217 isestablished, which discharges the parasitic capacitance of main switch106. Very shortly thereafter, at time t₆, the body diode of main switch106 becomes forward biased, as illustrated in schematic 208. (Note thatschematic 208 and schematic 200 depict the same switching stage.)Current 210 flowing through the body diode of main switch 106 allows formain switch 106 to close under zero voltage switching, and the cyclerepeats again beginning with time t₀ illustrated in schematic 201.

Because the operations described above all achieve zero voltageswitching of main switch 106 and auxiliary switch 107, there are no turnon switching losses associated with the operation of converter 100.Because switching losses are generally proportional to the frequency ofthe switching operation, this allows the converter to be operated athigher frequencies without undesirably increasing losses.

Turning back to FIG. 3, it can be appreciated that main switch 106 isthe primary control device for converter 100. The longer the on time Tonof main switch 106 (i.e., the longer the interval between main switch106 turn on at time t0 and turn off at time t2), the more energy will bestored in the magnetic field associated with primary coil 108 andsecondary coil 111. Conversely, auxiliary switch 107 is a freewheelingand recirculating switch that allows resonant operation of the primaryside. Auxiliary switch 107 has a duty cycle that is the complement ofthe duty cycle of main switch 106. In other words, when main switch 106is on, auxiliary switch 107 is off, and vice-versa (less the dead timesprovided between turning off one switch and turning on the other toprevent cross conduction, shorting out the DC bus, and causing damage tothe circuitry or other components).

The dead time required between switching events (t_(dead)) willgenerally be a function of the amount of time required to charge theparasitic capacitances associated with the main and auxiliary switches.Thus, for embodiments in which main switch 106 and auxiliary switch 107are MOSFETs, the drain to source capacitance CDs with drive the deadtime. In general, devices having higher current ratings will also havewider channels (to reduce the drain to source resistance R_(DS)), whichincreases C_(DS). Additionally, devices having higher voltage handlingwill require longer transition times (and thus longer dead times).Because the circuit must be able to transfer all energy stored themagnetic field during main switch 106's on time to the secondary duringthe main switch's off time, the duty cycle of auxiliary switch 107 will,in some embodiments, be longer than the duty cycle of main switch 106.This may result in auxiliary switch 107 being a physically largerswitch, and thus having a higher associated capacitance. Additionally,As a result, the dead time t_(dead) may be selected as a function of theparasitic capacitance associated with auxiliary switch 107.

With further reference to FIG. 3, one advantageous aspect of the primaryresonant flyback converter may be seen. Secondary current 304, which isthe current flowing from secondary coil 111 to load 220 is substantiallysinusoidal. This is in contrast to conventional flyback converters, inwhich the secondary current has a triangular shape. Having a sinusoidalsecondary current decreases higher harmonics of the primary switchingfrequency, and therefore reduces the amount of electromagneticinterference (EMI) that must be otherwise dealt with in the system.Reduced EMI may be advantageous when converter 100 used with certaintypes of systems, for example, those that employ capacitive touchsensors. Such capacitive touch sensing systems sometimes operate withfrequencies that are in the same general range as the switchingfrequency of power supplies, and the resulting EMI can interfere withtheir operation. The sinusoidal secondary current 304 depicted in FIG. 3can therefore improve the operation of such systems.

Additionally, implementation of zero voltage switching (as discussedabove) may improve the noise and EMI performance of power supply 100.Voltage waveform 305 depicts the voltage at the junction of main switch106 and auxiliary switch 107, i.e., the voltage applied to the input ofprimary coil 108. As can be seen at points 305 a and 305 b,implementation of zero voltage switching smoothens out the transitionfrom high voltage to low and low voltage to high as applied to primarycoil 108. Elimination of voltage spikes at these transitions can improveEMI performance of the circuit, because primary coil 108 and secondarycoil 111 can act as antennas for EMI.

FIG. 4 illustrates two alternative embodiments of primary resonantflyback converters employing minor circuit topology differences. Incircuit 401, resonant capacitor 409 has been relocated so as to becoupled between the DC bus 104 and primary winding 108. Additionally,main switch 106 and 107 have been reversed with respect to DC bus 104and ground. The switching schemes described herein functionsubstantially similarly in this embodiment, and the sequence ofoperation is generally as described with reference to FIG. 2, the onlydifference is the sequence of components with respect to DC bus 104 andground.

Circuit 402 represents a further variation in which the resonantcapacitor has been split into two separate capacitors 409 a and 409 bforming a half bridge with respect to DC bus 104 and ground. Primarycoil 108 is coupled between the junction point of the half bridge formedby main switch 106 and auxiliary switch 107 (as described above) and thejunction point of the half bridge formed by the resonant capacitors 409a and 409 b. As above, the switching scheme of main and auxiliaryswitches 106 and 107 remains generally as described.

One further advantage of the primary resonant flyback converter topologydescribed above is improved efficiency. In some embodiments, efficiencymay be improved from around 88% using a conventional flyback topology toaround 96% for a primary resonant flyback converter. This efficiencyimprovement may afford a number of advantages beyond reduced powerconsumption. For example, improving the efficiency may reduce thethermal load associated with main switch 106 and/or auxiliary switch 107to a value sufficiently low that they may be integrated into a singlephysical package with controller 110. This can improve both the cost ofsystems implemented in this way, as well as reducing the physicalfootprint (i.e., size) of the system.

II. Full Bridge Primary Resonant Flyback Converter

The half bridge primary resonant flyback converters described above canhave improved power conversion efficiency because of their incorporationof zero voltage switching. However, to incorporate zero voltageswitching, the range of suitable inductance values for primary coil 108is limited. In some cases, to accommodate zero voltage switching in aprimary resonant flyback converter, the inductance of primary coil 108may be fairly low as compared to the corresponding primary coilinductance value in a conventional discontinuous conduction mode flybackconverter. As a result of this lower inductance value, the impedance ofprimary coil 108 will be lower (at any given frequency), which mayresult in undesirably high magnetizing currents, particularly at highervoltage levels. This high magnetizing current may be addressed in partby increasing the frequency of operation at higher voltages (asdiscussed in greater detail below), but another solution may bedesirable in some embodiments.

In some embodiments, half bridge primary resonant flyback converters mayhave other disadvantages as well. For example, the voltage of DC bus 104must be divided across primary coil 108 and resonant capacitor 109. As aresult, the power conversion gain will always be less than one for ahalf bridge primary resonant flyback converter. The voltage acrossresonant capacitor 109 will be equal to the voltage of DC bus 104 timesthe switching duty cycle of main switch 106. As a result, the turnsratio between primary coil 108 and secondary coil 111 (i.e.,N_(p)/N_(s)) may also be constrained to a relatively small value. Insome operating conditions, this may result in high voltage stress on thesynchronous rectifier 112. Additionally, the duty cycle of main switch106 in a half bridge primary resonant flyback converter is limited to50% because the energy stored in the transformer is only transferredduring the off time of main switch 106 (i.e., the converter is inflyback operation). Beyond a 50% duty cycle for main switch 106, powerconversion gain of the converter will actually be decreasing.

These issues may be mitigated in some embodiments by employing a fullbridge primary resonant flyback converter. By switching the input stageto a full-bridge configuration, the power conversion gain can be higherthan one because the transformer voltage can be positive or negativewith respect to the voltage of DC bus 104. As a result, the turns ratiocan be increased thereby reducing voltage stress on the outputsynchronous rectifier 112, which allows lower voltage rated synchronousrectifiers to be used, providing increased efficiency. Also, because thepower conversion gain can be greater than one, the duty cycle of themain switches may be decreased relative to that of a half bridgedelivering the same power. Because of the foregoing, the inductance ofprimary coil 108 may be increased, increasing the associated magnetizingimpedance and decreasing the magnetizing currents. Reducing themagnetizing currents can also reduce circulating current losses on theprimary size and allow the use of a physically smaller transformer (ormutually coupled primary and secondary coils).

An exemplary full bridge primary resonant flyback converter 500 isillustrated in FIG. 5. Voltage and current sensing circuits and controlcircuits have been omitted for clarity. However, any of the varioussensing and control circuits discussed herein may be employed. As can beseen, the full bridge primary resonant flyback converter 500 uses fourswitching devices: high side main switch 506 a, low side main switch 506b, high side auxiliary switch 507 a, and low side auxiliary switch 507b. Primary coil 108 and resonant capacitor 109 are series coupledbetween the junction point of high side main switch 506 a and low sideauxiliary switch 506 b and the junction point of high side auxiliaryswitch 507 a and low side main switch 506 b.

Main switches 506 a and 506 b are switched together, and may be operatedaccording to any of the switching schemes described herein. It will beappreciated that the on time of the main switches can be lower whilestill delivering the same amount of power as a half bridge primaryresonant flyback converter. Auxiliary switches 507 a and 507 b areswitched together and are switched oppositely with respect to mainswitches 506 a and 506 b. As discussed elsewhere herein, there may be asuitable dead time between switching off the main switches and switchingon the auxiliary switches (and vice versa) to prevent cross conduction.

In some embodiments, operation as either a full bridge or half bridgeprimary resonant converter may be selected when using the topologyillustrated in FIG. 5. For example, full bridge or half bridge operationmay be selected in response to the voltage of DC bus 104. In the case ofa higher DC bus voltage, a lower conversion gain is required, and halfbridge operation may be selected. Conversely, in the case of a lower DCbus voltage, a higher conversion gain is required, and full bridgeoperation may be selected. This can allow operation of the converterwithout the extreme range of duty cycles that would otherwise berequired to accommodate a wide input voltage range. To configure theconverter illustrated in FIG. 5 as a half bridge primary resonantconverter, switch 507 a may be turned off (opened) while switch 506 b isturned on (closed). In that case, switch 506 a may be operated as themain switch, and switch 507 b may be controlled as the auxiliary switch.(It will be appreciated that, in this arrangement, the circuitillustrated in FIG. 5 becomes substantially equivalent to the circuitillustrated in FIG. 1, and operation is as described above.)

III. Primary Side Control

As discussed above with respect to FIG. 1, flyback converters may beimplemented with output voltage sensing and output voltage controlperformed on the secondary side of the converter. For example, asillustrated in FIG. 1, converter 100 has output voltage and control loop113 located on the secondary side of converter 100. This requires anoptocoupler 115 to provide feedback signal 114 to controller 110.Controller 110 can use feedback signal 114 to generate the drive signalsfor main switch 106 and auxiliary switch 107. Even if output voltagecontrol loop 113 b is implemented as part of controller 110 (i.e.,implemented on the primary side of the controller), the output voltagefeedback signal 114 is still required, which requires optocoupler 115 sothat galvanic isolation is provided between primary and secondary. Insome embodiments, it may be desirable to perform all output voltagesensing and output voltage control on the primary side of thecontroller. So doing can facilitate elimination of optocoupler 115 aswell as all sensing circuitry on the secondary side. This can provide anumber of advantages, including reduced size, reduced cost, improvedreliability. Additionally, system design may be simplified byeliminating the need to design around the optocoupler's non-linearcurrent transfer ratios and temperature dependencies.

FIG. 6 illustrates a primary resonant flyback converter 600 featuringprimary side control. Primary side 601 a of converter 600 includesprimary coil 108 and all components electrically connected thereto,including main switch 106, auxiliary switch 107, resonant capacitor 109,DC voltage bus 104 supported by capacitor 105, rectifier 103, and ACvoltage input 101. Secondary side 601 b or converter 600 includessecondary coil 111, synchronous rectifier 112, and output terminal 102for supplying a regulated DC voltage to a load (not shown). Each ofthese components operate generally as described above with respect toFIG. 1. Further, as discussed above, primary coil 108 may be the primarywinding of a transformer, or may be a mutual inductor magneticallycoupled to secondary coil 111.

As can be seen with reference to FIG. 6, a significant distinctionbetween primary side controlled primary resonant flyback converter 600and the primary resonant flyback converter 100 illustrated in FIG. 1 isthe absence of output voltage and control loop 113 from secondary side601 b of controller 600, as well as the optocoupler required to coupleits signal to controller 110 on the secondary side. Instead, converter600 implements all control of the converter in voltage/current controlloop 610, which is located on primary side 601 a of converter 600. To doso, voltage/current control loop 610 can obtain output voltage (and alsooutput current) information from resonant capacitor 109. (The followingdiscussion describes obtaining information about the output voltagepresented at output terminal 102 from resonant capacitor 109. Currentsensing techniques are described in greater detail below.)

FIG. 7 depicts two equivalent circuit schematics 701 and 702corresponding to two portions of the switching cycle for converter 600.More specifically, schematic 701 depicts the time interval between t3and t4, during which auxiliary switch 107 closes under zero voltageswitching while its body diode is conducting resonating primary sidecurrent 215 a in the forward direction through primary coil 108. Thistime interval and associated operations correspond to that describedabove with respect to schematic 205 in FIG. 2. Schematic 702 depicts thetime interval between t₄ and t₅, during which auxiliary switch 107 isclosed and conducting resonating primary side current in the reversedirection through primary coil 108. This time interval and associatedoperations correspond to that described above with respect to schematic206 in FIG. 2.

As seen in FIG. 7, because the voltage drop across auxiliary switch 107is negligible, the voltage across the primary coil 108 is equal to thevoltage across resonant capacitor 109. Additionally, the ratio betweenthe voltage across primary coil 108 and the voltage across secondarycoil 111 is equal to the ratio of the numbers of turns in the respectivecoils. Thus, the voltage across the resonant capacitor VCP isproportional to the output voltage, with the constant of proportionalitybeing the turns ratio. In other words:

$V_{CP} = {{- \frac{N_{P}}{N_{S}}}V_{out}}$

where V_(CP) is the voltage across resonant capacitor 109, N_(S) is thenumber of turns in secondary coil 111, N_(P) is the number of turns inprimary coil 108, and V_(out) is the output voltage.

It will be appreciated that the output voltage V_(out) is not exactlyequal to the voltage across secondary winding 111 because there is somevoltage drop across rectifier 112. However, in practice, this voltagedrop is small, and may be ignored in some cases. For example, slightvariations in output voltage regulation that occur due to the dropacross rectifier 112 may be sufficiently small as to not materiallyaffect operation of the circuit as a battery charger. Also, it will beappreciated that the error associated with neglecting the voltage dropacross rectifier 112 is larger when the output load current is high andsmaller when the output load current is low.

Instead of neglecting the voltage drop across rectifier 112, knowncharacteristics of rectifier 112 may be used to offset the sensedcapacitor voltage. For example, a conventional diode might have a onevoltage drop, while a Schottky diode might have a lower drop, and asynchronous rectifier may have a still lower voltage drop, all of whichwill be known to the system designer. The interface circuitry betweenresonant capacitor 109 and voltage/current control loop may be designedaccordingly to provide for these offsets, or voltage/current controlloop 610 may be altered to account for this information. The alternationmay be accomplished by appropriate design of the input circuitry, or, ifvoltage/current control loop is a digital or hybrid digital/analogcontroller, the digital portion of the control loop may be adjustedaccordingly. Alternatively or additionally, secondary side currentinformation may be further used to refine control of the output voltagebased on the sensed voltage across capacitor.

Thus, as illustrated in FIG. 6, voltage/current control loop 610 may useas an input the voltage across resonant capacitor 109, which is directlyproportional to the output voltage. Voltage/current control loop 610 maybe based on analog circuitry, digital circuitry, hybrid circuitry, etc.In addition to sensing and regulating the output voltage by adjustingthe timing and frequency of gate drive signals for main switch 106 andauxiliary switch 107, voltage/current control loop 610 may also senseand regulate output current as described in greater detail below.

In states other than those illustrated in schematics 701 and 702, theinstantaneous voltage across resonant capacitor 109 will not be directlyrelated to the output voltage. However, the average voltage acrossresonant capacitor 109 will be proportional to the output voltage. Foroutput voltage sensing during other states of the switching cycle (i.e.,the other switching states described above with reference to FIG. 2), alow pass filter may be connected between resonant capacitor 109 andvoltage/current control loop 610. Alternatively, a low pass input filtermay be integrated with control loop 610. In either case, low pass filtermay be implemented with analog circuitry, digital filtering, or acombination thereof. In all cases, this low pass filtered capacitorvoltage may be used as a control input for output voltage control duringthe remaining portions of the switching cycle. Additionally, loadvoltage may also be sensed even more accurately by sampling the resonantcapacitor voltage at specific timings.

In some embodiments, the design of converter 100 and voltage controlloop 610 may be such that the bandwidth of the overall system is on theorder of 1-10 kHz. The voltage across resonant capacitor 109 will have avoltage ripple at the switching frequency of the main switch 106, whichmay be on the order of 100 kHz. Therefore, even after low passfiltering, the resultant capacitor voltage signal will still besufficiently “fast” to not affect the dynamic response ofvoltage/current control loop 610, thereby allowing effective control ofconverter 100.

An additional advantage of sensing output voltage based on the voltageacross resonant capacitor 109 arises when implementing outputovervoltage protection control. In some conventional embodiments, outputvoltage is sensed on the secondary side and relayed via an optocouplerto the primary side switch driver, which can shut down the converterwhen an output overvoltage condition is detected. However, in cases inwhich the main voltage control loop resides on the secondary side, anerror signal is sent back to the primary side, not the output voltageitself. Thus, sending additional voltage information requires anotheroptocoupler, along with its associated cost, size, and reliabilityissues. Thus, sensing output voltage directly from the resonantcapacitor 109 can also eliminate this additional component in someembodiments.

FIG. 8 is a flow chart depicting a modified control scheme for a primaryresonant flyback converter using the resonant capacitor 109 to sense theoutput voltage as described above. As discussed above, the controlscheme may be implemented by controller 610 (FIG. 6) using analog,digital, or hybrid circuitry. The control process begins at 801 withsensing the voltage across the resonant capacitor. (Optional blocks 802and 807 relate to the current sensing features discussed below may bedisregarded.) The sensed voltage is then compared (803 a; 803 b) to theoutput voltage setpoint (i.e., the regulated output voltage of theconverter). If the output voltage is less than the setpoint (meaning theoutput voltage is low), the duty cycle of the main switch is increased(804 a). If the output voltage is greater than the setpoint (meaning theoutput voltage is high), the duty cycle of the main switch is decreased(804 b). In either case, the sensed voltage is also compared to anovervoltage threshold (805). If the output voltage is beyond theovervoltage threshold (indicating some sort of malfunction), theconverter is stopped (806). Otherwise, the process repeats withcontinued sensing of the output voltage (802).

IV. Lossless Current Sensing

In addition to sensing the output voltage as described above, suitablecontrol of converter 100 may require sensing one or more currentsflowing through the converter. In some embodiments, the primary sidecurrent flowing through primary coil 108 and resonant capacitor 109 maybe of interest. Conventional sensing techniques would use a senseresistor in series with the primary coil 108 and resonant capacitor 109.However, because the entire primary side current would be continuouslyflowing through such a resistor, overall efficiency of the converterwould be reduced. FIG. 9 illustrates an alternative current sensingarrangement that substantially reduces the losses associated withprimary current side sensing.

Converter 100 illustrated in FIG. 9 can generally correspond to thevarious embodiments described elsewhere herein. Additionally, a currentsense circuit 900 may be coupled in parallel with resonant capacitor109. Current sense circuit 900 can include a current sense capacitor 901and a voltage divider including resistors 902 and 903. Current sensecapacitor 901 can have a relatively small capacitance compared toresonant capacitor 109. This ensures that only a small fraction of theprimary current flows through current sense circuit 900. In someembodiments, the capacitance of 901 may be one tenth ( 1/10) thecapacitance of resonant capacitor 109. In other embodiments, thecapacitance of 901 may be even smaller, such as one one-thousandth (1/100). The inventor has implemented a version of the circuit using acapacitance ratio of one six-hundredth ( 1/600). Selection of a ratiofrom this range for a given embodiment can be performed based on theparticulars of the circuit's design and performance requirements.

Current sense circuit 900 also includes two very small resistors 902 and903, which form a voltage divider. The primary current can be sensed atterminal 904, which is the central point of this voltage divider. Theadvantage of a voltage divider arrangement is that the current sensinggain of the system may be selected by varying the values of the twosense resistors. However, as an alternative, only a single resistor 903could be used, with the primary current being sensed as the voltageacross this single resistor. The current sensing circuit 900 will have atime constant determined by the values of the sense capacitor 901 andsense resistor(s) 902 and 903. Thus, sense circuit 900 may be consideredto be a low pass filter having a cutoff frequency that is inverselyproportional to the product of the capacitance of sense capacitor 901and the total resistance of sense resistors 902 and 903. In other words,

$f_{cutoff} = \frac{1}{2\pi \; {C_{sense}\left( {R_{{sense}\; 1} + R_{{sense}\; 2}} \right)}}$

Thus, it may be desirable to select these values so that the cutofffrequency of the circuit is higher than the switching frequency. In someembodiments, the resistance and capacitance values may be selected sothat the cutoff frequency of current measurement circuit 900 is betweenten and one hundred times (10× to 100×) the switching frequency ofconverter 100. This will ensure that the sensing circuitry providessufficient frequency response to allow effective control of converter100.

FIG. 10 illustrates two sets of current traces from an embodiment of thecurrent sensing technique described above. Current trace 1001 is theprimary current for a primary resonant flyback converter operating at arelatively low input voltage. Current trace 1002 is the correspondingoutput of the current sensing circuit described above. Similarly,current trace 1003 is the primary current for the same converteroperating at a relatively higher input voltage with a higher switchingfrequency. Current trace 1004 is the corresponding output of the currentsensing circuit. As can be seen, the waveforms are substantiallyidentical, with the only deviations resulting from a slight lag orsmoothing of sharp transitions, due to the effects of thecapacitive-based sensing. These minor deviations are sufficiently smallthat they will not compromise effective control of the converter insome, or even many, embodiments. This may be, for example, because thecurrent sensing is used primarily for overcurrent protection, ratherthan precise control of switch timing, frequency, or duty cycle foroutput regulation.

Turning back to FIG. 8, the integration of current sensing as describedherein into the control loop is illustrated. At block 802, the primarycurrent is sensed (as described above). This current may be compared toan overcurrent threshold at block 807. If the sensed current is belowthe threshold, then the control loop continues as described above. Ifthe sensed current is above the overcurrent threshold, then theconverter is stopped at block 806. It will also be appreciated that thesensed current may be used for other controller tasks instead of or inaddition to overcurrent protection.

V. Switching Frequency Control

High power density AC-DC converters often include small size (i.e., highpower density) as a design constraint. One technique for increasingpower density is to increase the operating frequency, which can reducethe size of various passive components, such as the capacitors andinductors. However, switching losses are increased with increasedswitching frequency. In some embodiments switching losses may beaddressed by varying the switching frequency. Disclosed below arevarious techniques for active control of switching frequency to improveefficiency in various operating domains.

A. Load and Input Voltage Compensated Switching Frequency Control

The foregoing description of primary resonant flyback converteroperation has been premised on operation at a fixed switching frequency.Output voltage regulation is accomplished by variation of the duty cycleof main switch 106. In other words, output voltage regulation isachieved by varying the on time (T_(on), FIG. 3) of main switch 106,while the total switching cycle time (T_(sw), FIG. 3) remains constant(and is the reciprocal of the switching frequency). Although a primaryresonant flyback converter can have improved full load efficiency byreducing switching losses, low load efficiency may remain relativelyunimproved because low load losses are largely driven by the magnetizingcurrent that continuously circulates on the primary side of theconverter.

With reference to primary current curve 303 in FIG. 3, primary currentsegment 303 a corresponds to the portion of the switching cycle duringwhich main switch 106 is turned on and is related to the magnetizingcurrent associated with primary coil 108. The slope of current segment303 a is determined by two parameters: the inductance of primary coil108 and the DC bus voltage 104. More specifically, the slope is directlyproportional to the DC bus voltage 104 and inversely proportional to theinductance of primary coil 108. The peak value of this current is thusdetermined by the slope and duration of the on-cycle (i.e., the amountof energy required by the load).

In some embodiments, a system designer will select the inductance valueof primary coil 108 to accomplish the maximum required energy transferper cycle (i.e., maximum rated power) at the minimum permissible voltageof DC bus 104. The minimum permissible voltage of DC bus 104 is afunction of the minimum rated input voltage. However, selecting aninductor value sufficiently large to result in maximum power at minimumDC voltage may result in an inductor slope (and thus magnetizingcurrent) that is substantially higher at low load and maximum ratedinput voltage, if frequency is held constant. Put another way, theinductance of primary coil 108 determines the magnetizing current at anygiven frequency of operation. The AC impedance of the primary coil isproportional to the inductance of the coil and the frequency ofoperation. Because the same primary coil 108 is used for all loadconditions, the only way to vary the magnetizing current (and thus theassociated losses) is to vary the frequency of operation.

At low load conditions, it may be desirable to increase the switchingfrequency, thereby increasing the impedance of primary coil 108. Thiscan reduce the magnetizing current and corresponding switching losses.Reduction in switching losses can substantially improve low loadefficiency of the converter. Conversely, at high load conditions, it maybe desirable to decrease the switching frequency, thereby decreasing theimpedance of primary coil 109. This can increase the magnetizingcurrent, thereby allowing for decreased dead time for zero voltageswitching, which can, in turn, improve full load efficiency. Thus,primary resonant flyback converter embodiments may be constructed usingthe techniques described below to vary the frequency of operation of theconverter based on converter load.

As discussed above with respect to FIG. 1, voltage sensing and controlloop 113 can sense the voltage at output terminal 102 using voltagesensing circuitry 113 a. The sensed output voltage can be input into avoltage control loop 113 b to generate a feedback signal 114. Feedbacksignal 114 can then be used to vary the duty cycle of main switch 106 toregulate output voltage 102. By extension, this also controls thecomplimentary duty cycle of auxiliary switch 107. The duty cycles arecontrolled as a function of converter load, with higher loads resultingin an increased duty cycle for main switch 106, up to a duty cycle of50%.

Thus, feedback signal 114 is indicative of the load on converter 100,and may therefore be used to control the switching frequency of theconverter, as well as the duty cycles of main switch 106 and auxiliaryswitch 107. FIG. 11 illustrates an embodiment of a primary resonantflyback converter 100 incorporating variable frequency switchingcontrol. Unless otherwise noted, the various components of converter 100operate as described with respect to various other embodiments. Theoutput voltage of converter 100 is sensed at output terminal 102 byoutput voltage sensing circuit 113 a. The sensed output voltage signalis communicated to control loop 113 b, which generates a feedback signal114. Feedback signal 114 can be communicated to frequency control block1101, which determines the switching frequency as described in greaterdetail below.

Although FIG. 11 depicts an arrangement in which the output voltage issensed on the secondary side of the converter, variable frequencyswitching may also be implemented in cases in which the output voltageis sensed on the primary side as described above. Thus, the optocoupleror other component providing galvanic isolation between primary andsecondary has been omitted from the drawing for clarity, although it maybe included in the circuit as required.

Generally, frequency control block 1101 may be configured to provide anappropriate switching frequency and duty cycle as a function ofconverter load. As discussed above, low load conditions may call for anincrease in switching frequency, while high loads call for a decrease inswitching frequency. Thus, frequency control block 1101 may comprise twoanalog control loops that provide an output frequency drive signal and aduty cycle signal as a function of output load, derived from feedbacksignal 114. Alternatively, either or both control loops may beimplemented digitally, or using hybrid analog/digital circuitry. In someembodiments, the switching frequency may be inversely proportional tofeedback signal 114 (which is itself proportional to load current). Inother embodiments, the frequency control loop may include a lookup tablethat selects from a plurality of discrete frequencies based on themagnitude of feedback signal 114. The lookup table may be generatedbased on designed/calculated values, empirical testing, or a combinationthereof. The frequency and duty cycle control signals may be provided tocontroller 110, which generates the gate drive signals for main switch106 and auxiliary switch 107.

When implementing variable frequency switching, some additional signalor context may be desired to provide control of duty cycle and switchingfrequency. For example, the magnetizing current of primary coil 108 maybe kept constant by maintaining a constant voltage to frequency ratiobetween the voltage of DC bus 104 and the switching frequency. Moregenerally, the range of magnetizing current may be constrained byconstraining this voltage to frequency ratio. Thus, the voltage of DCbus 104 (which is a direct function of the AC input voltage) may used asa further input signal 1102 into frequency control block 1101. Thevoltage of DC bus 104 may be sensed by any of a variety of voltagesensing circuits, which are omitted from FIG. 11 for clarity. In suchembodiments, the DC bus voltage signal 1102 may be fed into a firstcontrol loop that outputs a frequency selection signal to controller110, wherein the voltage to frequency ratio is kept constant orconstrained to a desired range. Thus, an increase in DC bus voltage mayresult in a corresponding increase in switching frequency, while adecrease in DC bus voltage may result in a corresponding decrease inswitching frequency.

Feedback signal 114, which is a function of converter load may be usedsolely to control the duty cycle of main switch 106 (and, by extension,the complimentary duty cycle of auxiliary switch 107), while the DC busvoltage signal 1102 is used solely to control the switching frequency.Alternatively, a two input control loop may be implemented in which boththe DC bus voltage signal 1102 and the feedback signal 114 are used toselect output frequency. As above the switching frequency control loopand the duty cycle control loop may be implemented using analog,digital, or hybrid circuitry, lookup tables, and other controllerimplementations. In some embodiments, frequency control block 1101 maybe implemented using a two dimensional lookup table that providesswitching frequencies for various combinations of output load (derivedfrom feedback signal 114) and DC bus voltage (derived from DC voltagebus signal 1102). As above, the table values may be linear as a functionof input voltage, but will vary non-linearly as a function of load, andso may be derived by calculation, empirical testing, or a combinationthereof.

Although frequency control block 1101 has been depicted separately fromcontroller 110 and output voltage sensing block 113 a and output voltagecontrol loop 113 b, these components may be combined into a singlecontroller when output voltage sensing is performed on the primary sideof converter 100, as described above. Additionally, such controller 110may also receive a current signal from current sensing circuitry 900,also described above. In those embodiments, controller 110 may beconfigured to provide overcurrent protection or otherwise use the sensedcurrent as desired to control operation of converter 100. In someembodiments, the off time of main switch 106 may be controlled withreference to the sensed current from current sensing circuitry 900.

FIG. 12A depicts a flowchart illustrating a switching frequency controlalgorithm 1200 incorporating some of the features described above. Theswitching frequency control algorithm may be implemented by a singlecontroller, such as controller 110, voltage control loop 113 b, primaryside controller 610 (FIG. 6), or a combination of controllers such ascontrol loop 113 b and frequency controller 1101 illustrated in FIG. 11.As with the other control algorithms discussed herein, the controllersmay be implemented using analog circuitry, digital circuitry, or hybridanalog/digital circuitry.

Beginning at block 1201, the converter output voltage is sensed. Theoutput voltage may be sensed on the secondary side of the controller (asdepicted in FIG. 1, for example) or on the primary side of the converter(as depicted in FIG. 6, for example). Additionally, the converter loadis detected at block 1202. As discussed above, the converter load may besensed using feedback signal 114 or other suitable signal ormeasurement. In blocks 1203 a, 1203 b, 1204 a, and 1204 b, the sensedoutput voltage is used to control the duty cycle of main switch 106 asdiscussed above. In block 1207 a, the controller determines whether theload as increased. If so, the switching frequency may be decreased(block 1208 a). In block 127 b, the controller determines whether theload has decreased. If so, the switching frequency may be decreased. Inany case, control returns to (optional) block 1205 for overvoltageprotection as discussed above. Additionally, for sake of clarity,overcurrent protection has been omitted from FIG. 12, but it will beappreciated that an overcurrent loop as described above with respect toFIG. 8 (or other overcurrent protection loop) could also be included.

FIG. 12B depicts a flowchart illustrating an alternative switchingfrequency control algorithm 1210 based on sensing DC bus voltage (asdiscussed above). Like numbered control blocks function as describedabove. Algorithm 1210 senses DC bus voltage as indicated by connection1102 in FIG. 11 at block 1212. If the DC bus voltage has increased(block 1217 a), then the switching frequency may be increased (block1218 a) as discussed above. Alternatively, if the DC bus voltage hasdecreased (block 1217 b), the switching frequency may be decreased(block 1218 b). This can allow the voltage/frequency to be keptconstant, as discussed above.

As discussed above, the switching frequency control loop may be based ona combination of load sensing and input voltage sensing, in which casethe control loops 1200 and 1210 may be combined into a single controlloop. Additionally, the flow charts of FIGS. 12A and 12B are depictedgenerally to illustrate the underlying control concepts. It will beappreciated that the specifics of the control algorithm may vary fromimplementation to implementation and that variations on the illustratedflowcharts are possible.

B. DC Ripple Voltage Compensated Switching Frequency Control

Turning back to FIG. 11, it will be appreciated that DC bus 104 willhave a low frequency ripple corresponding to the frequency of AC inputpower source 101. It can further be shown that this ripple voltagevaries as a function of AC input voltage and load condition. Morespecifically, the ripple voltage will increase with decreases in the ACvoltage supplied and will also increase with increased load on theconverter. In some embodiments it may be desirable to limit this ripplevoltage.

Classical approaches to reducing ripple voltage have focused on DC buscapacitor 105. More specifically, increasing the size of capacitor 105will tend to decrease the ripple voltage. In many embodiments, capacitor105 may be the physically largest component in the circuit. It is notuncommon for a DC bus capacitor to take up 20˜40% of the volume of asmall AC-DC adapter. If a large ripple voltage is present because of asmaller DC bulk capacitor 105, this low frequency ripple voltage can beappear at the output voltage terminal. In some cases, it may bedifficult to eliminate this ripple voltage at the output because itsfrequency is too low. However, because physical size is often asignificant design constraint, it is generally desirable that capacitor105 (like the other components) be no larger than necessary.

In the power converter embodiments discussed herein, varying theswitching frequency of main switch 106 and auxiliary switch 107 can beused to help reduce the ripple voltage appearing at output terminal 102.In other words, the switching frequency of the main and auxiliaryswitches may be controlled as a function of DC ripple to minimize orreduce the low frequency ripple voltage appearing at output terminal102. Conceptually, this is very similar to the input voltage compensatedswitching frequency control discussed above. Recall that the voltage ofDC bus 104 may be used to select the switching frequency for main switch106 and auxiliary switch 107. Because ripple voltage is a component ofthe DC bus voltage, the frequency control techniques discussed above maybe tuned to also account for ripple voltage in selecting the outputfrequency.

The ripple voltage frequency is the same frequency as the AC powersupply (e.g., 50-60 Hz) for a half-bridge rectifier, or twice the ACpower supply frequency for a full bridge rectifier (e.g., 100-120 Hz).The switching frequency range of the converter will be chosen based on avariety of design constraints, but will usually be much higher (in thehundreds of kHz range) than the AC power supply frequency. Additionally,the ripple voltage frequency is usually much lower than the overallbandwidth of the control system for the converter. Thus, adapting the DCbus voltage controlled frequency selection discussed above to alsoaccount for ripple voltage may be achieved with relativelystraightforward tuning of the voltage-based frequency selectiontechniques described above. For simplicity, if the above describedcontrol technique is based on a steady state value of the DC busvoltage, adapting it for ripple control may be thought of as a slightlyfaster “real time” voltage based control. In some embodiments, thetable-based control described above may be expanded to a threedimensional table indicating an appropriate switching frequency as afunction of steady state DC bus voltage and ripple voltage.

C. Burst Mode Operation

As described above, the switching frequency of main switch 106 andauxiliary switch 107 may be varied as a function of load on theconverter to improve efficiency. More specifically, as the load on theconverter decreases, increasing the switching frequency can increase theimpedance of primary coil 101, thereby reducing the circulatingmagnetizing currents associated with the primary coil and reducingconduction losses associated with these circulating currents. However,there are practical limits on how much the switching frequency may beincreased. As load continues to decrease, it may be desirable totemporarily shut down switching of the converter. At that point, thereare no switching losses, nor any conduction losses, yet the low amountof load may still be powered by residual energy stored in the system,for example in the output capacitor. As this energy is used by the load,the output voltage (V_(out)) will begin to drop, triggering reactivationof switching in the circuit. This type of operation may be referred toas burst mode, i.e., the switching components are operated in burstsduring low load conditions.

As was discussed above, feedback signal 114 is indicative of the outputload on the converter and, in at least some embodiments, may beproportional to load current. In other words, high load levels willresult in a high level of feedback signal 114, while low loads willresult in a low level of feedback signal 114. Thus, feedback signal 114may be used to control the burst mode operation of converter 100. Insome embodiments, a hysteretic control algorithm may be used. In someembodiments, the hysteretic control algorithm may be implemented byadditional circuitry and/or programming in frequency controller 1101.Alternatively, an additional burst mode controller may be provided, orthe burst mode controller may be implemented with one of the othercontrol components.

The hysteretic control algorithm for burst mode control may beconfigured to operated as follows and illustrated in FIG. 15. A highthreshold and low threshold may be selected for feedback signal 114. Thehigh threshold may correspond to the load condition at which switchingshould be enabled. The low may correspond to the load level at whichswitching should be disabled. When load on the converter decreases tothe low load threshold (152 a), switching of main switching device 106and auxiliary switching device 107 may be disabled (1503 a). As feedbacksignal 114 increases to the high threshold (1502 a), switching of mainswitching device 106 and auxiliary switching device 107 may bere-enabled (1503 b). Once switching is re-enabled, the switching maytake place at a fixed frequency or at a variable frequency as describedabove.

FIG. 13 illustrates pertinent waveforms associated with burst modeoperation. Signal 1303 represents the instantaneous value of feedbacksignal 114. Starting at time t₀, switching is disabled. As the outputvoltage 1306 decreases to its minimum output voltage threshold 1307 b,feedback signal 1303 correspondingly increases until it reaches highthreshold 1302 a. This triggers enabling of switching, which can be seenin drive signal 1304 for main switch 106 and drive signal 1305 forauxiliary switch 107. Additionally, signal 1301 indicates whetherswitching is enabled or disabled, and thus may be seen to transitionhigh in region 1301 b, corresponding to the activation of switching.Because the load on the converter is relatively light, after a shorttime interval ending at time t₂, output voltage 1306 can be seen to haverecovered to its maximum value 1307 a. Corresponding feedback signal1303 has decreased to low threshold 1302 b, which triggers deactivationof switching, as may be seen in signals 1301, 1304, and 1305. Then, fromtime t₂ to time t₃, the output voltage decreases (at a rate determinedby the load) until the output voltage again reaches output voltageminimum threshold 1307 b, at which time corresponding feedback signal1303 has again reached high threshold 1302 a, and the cycle repeats.

Because the resonant circuit (and particularly resonant capacitor 109)may be completely discharged as a result of burst mode operation,resuming switching operations may result in a high current spikeassociated with recharging the resonant capacitor. Thus, in someembodiments, it may be desirable to have a soft start of the switchingoperations. This may be achieved, for example, but slowly increasing theduty cycle of main switch 106 over the first several switching cycleswhen switching is re-enabled (1503 b; FIG. 15). Pertinent waveforms forsuch an embodiment are illustrated in FIG. 14. Switching enable signal1301 transitions to high state 1301 b, indicating the onset of switchingoperations. Main switch 106 drive signal 1404 is controlled so as toprovide a sequence of gate drive pulses 1404 a, 1404 b, 1404 c, 1404 d,1404 e, and 1404 f of increasing duration. (Recall that auxiliary switch107 is driven with an opposite duty cycle that allows for some deadtime.) This results in the primary current waveform 1408 and secondarycurrent waveform 1409 illustrated, in which the RMS primary currentgradually increases and the secondary current pules gradually increasein width. This results in a smoother transition from the switchingdisabled state to the switching enabled state.

In some embodiments, it may be desirable to transition from continuousswitching operation to burst mode switching operation such that theinitial burst mode of operation will result in a relatively longswitching enabled duration with a relatively short switching disabledtime. This may be achieved by adjusting the high threshold for feedbacksignal 114. In some embodiments, the transition to burst mode operationmay occur at around 50% load, although this transition could also occurbetween 40% to 50% load, or at even lower loads, such as 20% to 40%. Anytransition point may be selected by a designer based on the particulargoals and requirements of a particular system. Another factor toconsider in implementing burst mode operation is that certain burstfrequencies may result in audible noises. Thus, the burst mode frequencyor range of frequencies may be selected so as to be outside the range ofhuman hearing (roughly 20 Hz to 20 kHz). This may also affect thetransition load at which burst mode operation is implemented.

V. Power Factor Corrected/Boost Topology

Flyback converters are used in a variety of applications, such as ACadapters for personal electronic devices with power ratings ranging from5 W (or sometimes less) up to 100 W (or sometimes more). However, oncethe power rating of a converter is higher than 65 W, applicableregulations (or even good engineering practice) may dictate that theconverters include some form of power factor correction.

Power factor is a measure of load reactance and is defined as the cosineof the phase difference between the voltage supplied and the currentdelivered. A purely resistive load will have the current in phase withthe voltage and will thus have a power factor of 1. A purely capacitiveload supplied with a fixed frequency AC voltage will have the currentleading the voltage by 90 degrees and will thus have a leading powerfactor of 0. A purely inductive load supplied with a fixed frequency ACvoltage will have the current lagging the voltage by 90 degrees, andwill thus have a lagging factor of 0. Loads with a resistive and netinductive component will have a lagging power factor between 0 and 1.Loads with a resistive and net capacitive component will have a leadingpower factor between 0 and 1.

The various converter topologies discussed above will generally presenta leading power factor because the DC bus capacitor 105 is directlypresented to the input power source 101. In practice, the power factorwill vary as a function of load and DC bus capacitor size, but a leadingpower factor is generally expected. It would be desirable for a flybackconverter to present an additional inductive load component to the powersource 101 that could balance out the capacitive component presented byDC bus capacitor 105. Previous converters requiring power factorcorrection have inserted a power factor correction stage in front of themain converter stage. In some implementations of such two-stage circuitsthe power factor correction stage may be expected to operate with anefficiency of approximately 95%, while the converter stage also operatesat a peak efficiency around 95%. Thus, the overall efficiency of thecircuit is reduced to something in the range of 90% or less. It wouldthus be desirable to integrate the power factor correction inductor withthe remainder of the power converter to achieve higher efficiency.

FIG. 16 depicts an embodiment of a power factor corrected primaryresonant flyback converter 1600 that includes input inductor 1601. Theinput inductor 1601 may be used for power factor correction and alsoinput voltage boosting as described further below. Power factorcorrected primary resonant flyback converter 1600 includes similarcomponents to the various embodiments described above, which arenumbered the same. FIG. 16 also shows various differences between thepower factor corrected primary resonant flyback converter 1600 and thevarious embodiments described above. First, input inductor 1601 iscoupled to the output of rectifier 103 and coupled to the junction ofmain switch 1606 and auxiliary switch 1607. Second, DC bus capacitor 105is coupled to the input through input inductor 1601 and body diode ofauxiliary switch 1607. Third, main switch 1606 and auxiliary switch 1607have been reversed, so that auxiliary switch is coupled to the DCvoltage bus 104 and main switch is coupled to ground. Finally, primarywinding 109 and resonant capacitor 108 are coupled between DC bus 104and the junction of main switch 1606 and auxiliary switch 1607 (ratherthan the junction and ground as in most embodiments described above). Itwill be appreciated that this arrangement is generally similar toconverter 401, illustrated in FIG. 4 and discussed above.

FIGS. 17 and 18 illustrate the switching sequence of the power factorcorrected primary resonant flyback converter 1600. FIG. 17 illustrates aseries of schematics depicting the equivalent circuit of the converterat various points during the switching cycle. FIG. 18 illustratespertinent waveforms and times during the switching cycle. Schematic 1700in FIG. 17 depicts the circuit just prior to turning on main switch 1606(i.e.,just prior to time to). Main switch 1606 and auxiliary switch 1607are depicted throughout FIG. 17 as their respective equivalent circuits,each comprising a parallel connected switch, body diode, and drain tosource capacitance. Just prior to main switch 1606 closing, current 1710is flowing through the body diode of switch 1606, resonant capacitor109, and primary winding 108 to charge DC bus capacitor 105. Becausecurrent is flowing through the body diode of main switch 1606, the mainswitch closure at time to is a zero voltage switching (ZVS) event,thereby reducing the switching losses associated with operation of thecircuit.

When main switch 1606 closes at time to, for a short period of time,current will continue flowing upward through primary winding 108 for abrief period of time before reversing. The reversal of this currentoccurs at time t₁. Schematic 1701 depicts the circuit during the timeperiod beginning at t₁ and extending until main switch 1606 is opened attime t₂. During this time period, there are two currents on the primaryside of the converter. A first current 1711 a flows from DC buscapacitor 105, through primary winding 108, resonant capacitor 109, andmain switch 1606 to ground/back to DC bus capacitor 105. A secondcurrent 1711 b flows from the rectified power source 1706, through inputinductor 1601 and main switch 1606 to ground/back to rectified powersource 1706. The combined current through main switch 1606 is thus thesum of currents 1711 a and 1711 b.

At time t₂ main switch 1606 opens. There is a brief dead time t_(dead)before auxiliary switch 1607 closes at time t₃. (The nature and purposeof this dead time were discussed above.) Equivalent circuit 1702 depictsthe converter during the time period between t₂ and t₃. There are twoprimary side currents during this time period. A first primary sidecurrent 1712 a is the continued current flow through primary winding108, which passes through resonant capacitor 109, body diode ofauxiliary switch 1607, and DC bus capacitor 105, back to ground. Thiscurrent recharges DC bus capacitor 105 with a portion of the energy thatwas stored in primary winding 108. The second primary side current 1712b is the continued current flow through input inductor 1601, whichpasses through the body diode of auxiliary switch 1607 and DC buscapacitor 105, back to ground. This current recharges DC bus capacitor105 with a portion of the energy that was stored in input inductor 1601.Because these currents are flowing through the body diode of auxiliaryswitch 1607, the closure of auxiliary switch 1607 at time t₃ can be azero voltage switching (ZVS) event. Also during this time period,secondary side current 1712 c begins to flow through rectifier 112 toload 220 and also charging output capacitor 221.

At time t₃, auxiliary switch 1607 closes. The time period beginning attime t₃ and extending until time t₄ (when the energy stored in inputinductor 1601 has been completely transferred to DC bus capacitor 105)is depicted in schematic 1703. As before, there are two currents on theprimary side of the converter. A first primary side current 1713 a isthe continued current flow through primary winding 108, which passesthrough resonant capacitor 109, now closed auxiliary switch 1607, and DCbus capacitor 105, back to ground, recharging DC bus capacitor 105 witha portion of the energy that was stored in primary winding 108. Thesecond primary side current 1713 b is the continued current flow throughinput inductor 1706, which passes through now closed auxiliary switch1607 and DC bus capacitor 105, back to ground, recharging DC buscapacitor 105 with a portion of the energy that was stored in inputinductor 1601. Also during this time period, secondary side current 1713c continues to flow through rectifier 112 to load 220 and also chargingoutput capacitor 221.

Schematic 1704 depicts the time period beginning at time t₄ (when theenergy stored in input inductor 1601 has been completely discharged) andextending until time t₅, when auxiliary switch 1607 is opened. Duringthis time period current 1714 reverse circulates through primary winding108, resonant capacitor 109, and auxiliary switch 1607 (due toresonance). Schematic 1705 depicts the time period beginning at time t₅(when auxiliary switch 1607 opens) and extending until time t₆, whichcorresponds to time t₀, i.e., the time at which main switch 1606 closesagain. The currents circulating on the primary side were described abovewith respect to schematic 1700.

As noted above, FIG. 18 depicts various circuit waveforms during theswitching cycle of the power factor corrected primary resonant flybackconverter. Waveform 1801 depicts the drive signal for main switch 1606.In the illustrated embodiment, drive signal 1801 is high when mainswitch 1606 is on (from time t₀ to time t₂) and low when main switch1606 is off (from time t₂ to t₆). It will be appreciated that if ap-channel switch were used, drive signal would be low/on and high/off.Similarly, waveform 1802 illustrates the drive signal for auxiliaryswitch 1607, which is on from time t₃ to time t₅. FIG. 18 alsoillustrates the dead time t_(dead) between time t₂ when main switch 1606is switched off and time t₃ when auxiliary switch 1607 is switched on.

Waveform 1803 illustrates the current through primary winding 108 duringthe switching cycle. Features of this waveform include: the regionbetween t₀ and t₁ when the current through primary winding 108 has notyet switched to the positive direction; the linear ramp up of primarycurrent during the on time of main switch 1606 between time t₀ and t₁;and the resonance of the primary current during the period t₂ to t₆ whenmain switch 1606 is open, including the brief increase and reversalassociated with total discharge of the input inductor 1601 at time t₄.Waveform 1804 illustrates quasi-sinusoidal current through secondarywinding 111 discussed above. Finally, waveform 1804 illustrates thevoltage appearing across the combination of primary winding 108 andresonant capacitor 109 during the switching cycle. In short, when mainswitch 1606 is closed, the full DC bus voltage appears across thecombination. When main switch 1606 is closed (and auxiliary switch 1607is opened) the voltage across the combination of these two components iszero (because they have equal and opposite voltages across each otherduring the resonant phase).

As discussed with respect to other embodiments, the duty cycle of mainswitch 1606 is controlled as a function of output load. Morespecifically, higher loads will result in higher duty cycles (up to aduty cycle of 50% for the half bridge configuration illustrated in FIG.16). As will be appreciated, main switch also controls the operation ofinput inductor 1601 (as distinguished from prior art embodiments inwhich a separate boost converter and/or power factor correction circuitmight be used to input into a flyback converter). Thus, while inputinductor 1601, main switch 1606, and body diode of auxiliary switch 1607form a boost converter, the output of which is delivered to DC buscapacitor 105, separate boost control is not required.

Because the converter is operated to provide a regulated output voltagewithout regard to the input voltage, the duty cycle of main switch 1606self-compensates for the different input voltages. However, in someembodiments it might be desirable to add additional circuitry to preventvoltage runaway of the boosted voltage appearing at the downstreamterminal of input inductor 1601. In some embodiments, this additionalcircuitry may be additional control circuitry that alters the switchingof main and/or auxiliary switches 1606 and 1607 (which may be analog,digital, or hybrid control circuitry). In other embodiments, thisadditional circuitry may be some form of clamping circuitry.Additionally, a combination of additional control circuitry andadditional clamping circuitry could be provided.

It will further be appreciated that operation of the circuit asdescribed above will result in a much improved power factor and smoothercharging currents (because of elimination of the current spikesassociated with presenting DC capacitor to the input power source). Insome embodiments, the input inductor size may be selected so as toprovide near unity power factor operation over a desired operatingrange.

Conclusion

Described above are various features and embodiments relating to primaryresonant flyback converters. Such converters may be used in a variety ofapplications, but may be particular advantageous when used inconjunction with power adapters and/or battery chargers for portableelectronic devices such as mobile telephones, smart phones, tabletcomputers, laptop computers, media players, and the like as well as theperipherals associated therewith. Such associated peripherals caninclude input devices (such as keyboards, mice, touchpads, tablets, andthe like), output devices (such as headphones or speakers), storagedevices, or any other peripheral.

Additionally, although numerous specific features and variousembodiments have been described, it is to be understood that, unlessotherwise noted as being mutually exclusive, the various features andembodiments may be combined in any of the various permutations in aparticular implementation. Thus, the various embodiments described aboveare provided by way of illustration only and should not be constructedto limit the scope of the disclosure. Various modifications and changescan be made to the principles and embodiments herein without departingfrom the scope of the disclosure and without departing from the scope ofthe claims.

1. A primary resonant flyback converter comprising: a primary winding; a secondary winding magnetically coupled to the primary winding and electrically coupled to an output rectifier, and an output terminal; a resonant capacitor coupled to the primary winding; a main switch configured to switch on to energize the primary winding to switch off to transfer energy stored in the primary winding to the secondary winding; an auxiliary switch configured to switch on during an off time of the main switch to allow a resonant current to circulate through the primary winding and the resonant capacitor; and a control circuit configured to operate the main switch and the auxiliary switch to produce a desired voltage at the output terminal.
 2. The primary resonant flyback converter of claim 1 wherein the control circuit is configured to operate the main switch and the auxiliary switch responsive to a voltage measured across the resonant capacitor.
 3. The primary resonant flyback converter of claim 2 wherein the voltage measured across the resonant capacitor is an instantaneous voltage.
 4. The primary resonant flyback converter of claim 2 wherein the voltage measured across the resonant capacitor is an average voltage.
 5. The primary resonant flyback converter of claim 2 wherein the control circuit is further configured to implement output overvoltage protection based on the voltage measured across the resonant capacitor.
 6. The primary resonant flyback converter of claim 1 wherein the control circuit is configured to: vary a duty cycle of the main switch and the auxiliary switch to produce a desired voltage at the output terminal; and vary a switching frequency of the main switch and the auxiliary switch responsive to a change in output load on the primary resonant flyback converter in combination with at least one of an input voltage into the primary resonant flyback converter and a DC bus voltage of the primary resonant flyback converter.
 7. The primary resonant flyback converter of claim 6 wherein the control circuit is configured to vary the switching frequency by increasing the switching frequency responsive to a decrease in output load or by decreasing the switching frequency responsive to an increase in output load.
 8. The primary resonant flyback converter of claim 6 wherein the control circuit is configured to vary the switching frequency of the main switch and the auxiliary switch responsive to both the change in output load and the input voltage.
 9. The primary resonant flyback converter of claim 6 wherein the control circuit configured to vary the switching frequency of the main switch and the auxiliary switch responsive to the DC voltage bus of the primary resonant flyback converter is further configured to vary the switching frequency of the main switch and the auxiliary switch responsive to a voltage ripple on the DC voltage bus.
 10. The primary resonant flyback converter of claim 1 wherein the control circuit is configured to implement a hysteretic control algorithm to temporarily disable and re-enable operation of the main switch and the auxiliary switch responsive to a decrease in output load on the primary resonant flyback converter.
 11. The primary resonant flyback converter of claim 10 wherein the control circuit is configured to re-enable operation of the main switch and the auxiliary switch responsive to an increase in output load.
 12. The primary resonant flyback converter of claim 11 wherein the hysteretic control algorithm references a high threshold corresponding to a load condition at which switching should be enabled and a low threshold corresponding to a load condition at which switching should be disabled.
 13. The primary resonant flyback converter of claim 12 wherein the high and low thresholds are compared to a feedback signal from the output voltage control loop.
 14. A primary resonant flyback converter comprising: a primary winding; a secondary winding magnetically coupled to the primary winding and electrically coupled to a rectifier, and an output terminal; a resonant capacitor coupled to the primary winding; a main switch configured to switch on to energize the primary winding from a DC voltage bus; an auxiliary switch configured to switch on during an off time of the main switch to allow a resonant current to circulate through the primary winding and the resonant capacitor; and a control circuit configured to operate the main switch and the auxiliary switch responsive to a sensed output voltage and further configured to sense a current through the primary coil using a current sense circuit coupled in parallel with the resonant capacitor, the current sense circuit comprising a sense capacitor and at least one sense resistor.
 15. The primary resonant flyback converter of claim 14 wherein a cutoff frequency of the current sense circuit is configured to be higher than a switching frequency of the primary resonant flyback converter.
 16. The primary resonant flyback converter of claim 14 wherein the control circuit is further configured to use the sensed current through the primary coil for overcurrent protection.
 17. The primary resonant flyback converter of claim 14 wherein the control circuit is further configured to: vary a duty cycle of the main switch and the auxiliary switch to produce a desired voltage at the output terminal; and vary a switching frequency of the main switch and the auxiliary switch responsive to a change in output load on the primary resonant flyback converter in combination with at least one of an input voltage into the primary resonant flyback converter and a DC bus voltage of the primary resonant flyback converter.
 18. The primary resonant flyback converter of claim 17 wherein the control circuit is configured to vary the switching frequency of the main switch and the auxiliary switch responsive to both the change in output load and the input voltage.
 19. The primary resonant flyback converter of claim 17 wherein the control circuit configured to vary the switching frequency of the main switch and the auxiliary switch responsive to the DC voltage bus of the primary resonant flyback converter is further configured to vary the switching frequency of the main switch and the auxiliary switch responsive to a voltage ripple on the DC voltage bus.
 20. The primary resonant flyback converter of claim 14 wherein the control circuit is configured to implement a hysteretic control algorithm to temporarily disable and re-enable operation of the main switch and the auxiliary switch responsive to a decrease in output load on the primary resonant flyback converter.
 21. A method of operating a primary resonant flyback converter, the method comprising: switching a main switch responsive to a sensed output voltage, wherein closing the main switch energizes a primary coil and opening the main switch transfers energy stored in the primary coil to a load electrically connected to a secondary coil magnetically coupled to the primary coil; and switching an auxiliary switch complimentarily to the main switch, wherein closing the auxiliary switch allows a resonant current to circulate through the primary coil and a resonant capacitor; wherein the main switch and the auxiliary switch are operated to produce a desired voltage at an output terminal.
 22. The method of claim 21 wherein the sensed output voltage is a voltage across the resonant capacitor.
 23. The method of claim 21 wherein the voltage across the resonant capacitor is an instantaneous voltage.
 24. The method of claim 21 wherein the voltage across the resonant capacitor is an average voltage.
 25. The method of claim 21 further comprising implementing output overvoltage protection for the primary resonant flyback converter responsive to the voltage across the resonant capacitor.
 26. The method of claim 21 further comprising sensing a current through the primary coil using a current sense circuit coupled in parallel with the resonant capacitor, the current sense circuit comprising a sense capacitor and at least one sense resistor.
 27. The method of claim 26 further comprising implementing overcurrent protection for the primary resonant flyback converter responsive to the sensed current.
 28. The method of claim 21 further comprising: varying a duty cycle of the main switch to produce a desired output voltage; and varying a switching frequency of the main switch responsive to the load on the converter in combination with at least one of an input voltage into the converter and a DC voltage bus of the converter
 29. The method of claim 28 wherein varying the switching frequency of the main switch responsive to at least one of the load on the converter and the input voltage into the converter comprises varying the switching frequency responsive to both the load and the input voltage.
 30. The method of claim 28 wherein varying the switching frequency of the main switch responsive to the DC voltage bus of the converter further comprises varying a switching frequency of the main switch responsive to a ripple voltage on a DC bus of the converter.
 31. The method of claim 28 wherein varying a switching frequency of the main switch responsive to the load on the power converter comprises temporarily disabling operation of the main switch responsive to a decrease in output load on the power converter.
 32. The method of claim 31 further comprising re-enabling operation of the main switch responsive to an increase in output load on the power converter. 